Dear Sirs and Madams, I have some problem with Fir Compiler II. When i set max number of channels 2, Clock Rate 120MHz and Input Sample Rate 60MSPS filter works perfect but when i change input sample rate to 1MSPS the results are invalid. Maybe somebody know something about this? Maybe somebody have working example with multiple channels and single wire? I check on quartus II 15.0 and quartus prime and on arria v and cyclone v devices. Best regards Adam

When you say that the results are "invalid", what exactly do you mean? The input/output signaling will be significantly different if you change the input sample rate. I don't know if you mean that the MATLAB sims are invalid or if the hardware was not behaving. In the latter case, you will need to create signaling in and out that will have quite a few blank spaces when changing from 60MSPS to 1MSPS. That is a ratio of 1/2 to 1/120. I find the info below to be pretty valuable when coming up with interface logic. After compiling the design, you can right-click on the FIR filter and select "Help...". The following info will appear. This happens to be for a 4-channel DUC (interpolation = 2). In your case, I believe you would see something like the following. It can be used as a baseline for interface logic. 60MSPS: <c0><c1> (repeats every 2) 1MSPS: <c0><c1><--><--><--116 more--> (repeats every 120) [FROM MY DESIGN / DUC INT=2]: Input Data Format (Repeats every 48 clock cycles) <c0><c1><c2><c3><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--> Output Data Format (Repeats every 24 clock cycles) <c0><c1><c2><c3><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--> If your data looks bad in the simulations, you might need a down/upsample block from simulink to make the FFT, etc look good. Jeff

Dear Sir, thank you for reply. Of course i take care about blank spaces between data as you wrote. When i say invalid i mean that impulse response from filter is invalid. For example coeffs are 1, 5, 5, 5, 5, 5 1 and impuls impuls response is same like coeffs when i set 60MSPS. When i change to 1MSPS the response is invalid only one coefficient value appears. I dont want to use decim or interpolate. Just filter two channels. Of course hardware not behaving. http://www.alteraforum.com/forum/attachment.php?attachmentid=12340&stc=1 Best regards Adam

Dear Sir, thank you for reply. Of course i take care about blank spaces between data as you wrote. When i say invalid i mean that impulse response from filter is invalid. For example coeffs are 1, 5, 5, 5, 5, 5 1 and impuls impuls response is same like coeffs when i set 60MSPS. When i change to 1MSPS the response is invalid only one coefficient value appears. I dont want to use decim or interpolate. Just filter two channels. Of course hardware not behaving. http://www.alteraforum.com/forum/attachment.php?attachmentid=12342&stc=1 Can you show me screen from simulation or signal tap how you control SOP EOP and valid signal? Best regards Adam

when you set data rate that is not same as clock rate you need to raise valid input pulses one every data sample(zero otherwise). e.g. for 1 Msps on 120Mhz clock then you pulse it once every 120 clocks (or once every 60 clocks if two channels).

Dear Sir, i do what you say but there is same problem. Can you Sir upload some screen from simulation or signal tap how to exacly control SOP, EOP and valid sink signals? Maybe i do something wrong. Best Regards Adam

Multichannel Fir Compiler ii problem.

19 Replies

Altera_Forum
Honored Contributor
10 years ago
When you say that the results are "invalid", what exactly do you mean? The input/output signaling will be significantly different if you change the input sample rate. I don't know if you mean that the MATLAB sims are invalid or if the hardware was not behaving. In the latter case, you will need to create signaling in and out that will have quite a few blank spaces when changing from 60MSPS to 1MSPS. That is a ratio of 1/2 to 1/120. I find the info below to be pretty valuable when coming up with interface logic. After compiling the design, you can right-click on the FIR filter and select "Help...". The following info will appear. This happens to be for a 4-channel DUC (interpolation = 2). In your case, I believe you would see something like the following. It can be used as a baseline for interface logic.

60MSPS:
<c0><c1> (repeats every 2)
1MSPS:
<c0><c1><--><--><--116 more--> (repeats every 120)

[FROM MY DESIGN / DUC INT=2]:
Input Data Format (Repeats every 48 clock cycles)
<c0><c1><c2><c3><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><-->
Output Data Format (Repeats every 24 clock cycles)
<c0><c1><c2><c3><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><-->

If your data looks bad in the simulations, you might need a down/upsample block from simulink to make the FFT, etc look good.

Jeff
Altera_Forum
Honored Contributor
10 years ago
Dear Sir,
thank you for reply. Of course i take care about blank spaces between data as you wrote.
When i say invalid i mean that impulse response from filter is invalid. For example coeffs are 1, 5, 5, 5, 5, 5 1 and impuls impuls response is same like coeffs when i set 60MSPS. When i change to 1MSPS the response is invalid only one coefficient value appears. I dont want to use decim or interpolate. Just filter two channels. Of course hardware not behaving.

http://www.alteraforum.com/forum/attachment.php?attachmentid=12340&stc=1

Best regards
Adam
multiple-attachments.zip82 KB
Altera_Forum
Honored Contributor
10 years ago
Dear Sir,
thank you for reply. Of course i take care about blank spaces between data as you wrote.
When i say invalid i mean that impulse response from filter is invalid. For example coeffs are 1, 5, 5, 5, 5, 5 1 and impuls impuls response is same like coeffs when i set 60MSPS. When i change to 1MSPS the response is invalid only one coefficient value appears. I dont want to use decim or interpolate. Just filter two channels. Of course hardware not behaving.
http://www.alteraforum.com/forum/attachment.php?attachmentid=12342&stc=1

Can you show me screen from simulation or signal tap how you control SOP EOP and valid signal?

Best regards
Adam
multiple-attachments.zip82 KB
Altera_Forum
Honored Contributor
10 years ago
when you set data rate that is not same as clock rate you need to raise valid input pulses one every data sample(zero otherwise). e.g. for 1 Msps on 120Mhz clock then you pulse it once every 120 clocks (or once every 60 clocks if two channels).
Altera_Forum
Honored Contributor
10 years ago
Dear Sir,
i do what you say but there is same problem.
Can you Sir upload some screen from simulation or signal tap how to exacly control SOP, EOP and valid sink signals? Maybe i do something wrong.

Best Regards
Adam
Altera_Forum
Honored Contributor
10 years ago
--- Quote Start ---
Dear Sir,
i do what you say but there is same problem.
Can you Sir upload some screen from simulation or signal tap how to exacly control SOP, EOP and valid sink signals? Maybe i do something wrong.

Best Regards
Adam
--- Quote End ---

I am not familiar with sop/eof for filters(but for fft) so can you ell me what is filter frame? I will send samples of two channels successively one after other. I know you can split them into frames but why?
Altera_Forum
Honored Contributor
10 years ago
It is not necessarily to use sop/eof and all this frame signals? Only first sop? I dont know what you think about filter frame?
Altera_Forum
Honored Contributor
10 years ago
I have done filters (and fir compiler) but only needed (data, valid input and possibly channel number). I don't know of any meaning for frames as filtering is not frame based but continuous stream. So what does the tool say about sop/eop? I don't know. You are using them so you need to clear that.
Altera_Forum
Honored Contributor
10 years ago
Documentation say i need sop/eop and valid. When i use only one channel there is no sop eop but when i change to more chanels then i have sop eop and valid. I do evrythink like in documentation but result i wrong when i use les than 60MSPS.
Altera_Forum
Honored Contributor
10 years ago
I assume sop is first channel, eop is last channel (as if you are giving channel number that way)

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Multichannel Fir Compiler ii problem.

19 Replies

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