Occasional ContributorHi,
i have ArriaV, DDR3 chips, but after deassert global and soft resets mem_reset_n stay is low. Soft reset generate after 1000 tick on 100MHz clk
What else can affect this signal?
Regular ContributorHi Sir,
I'm Adzim. Thanks for using Intel Community.
According to the KDB here, it's looks like the global and soft resets can only trigger the mem_reset_n signal.
Are you using the example design in your simulation?
If not, can you simulate your IP with the example design?
Which Quartus software that you used?
Regards,
Adzim
Occasional ContributorRegular ContributorHave you try to simulate your IP with the example design in your simulation?
Occasional ContributorAt the moment, no, since there were no problems when using the core on Cyclone 5
Regular ContributorCan you give it a test?
So before this you're working on Cyclone V device and it's worked.
But now you try to implemented it in Arria V is it?
Do you create a new IP for the Arria V or you use the existing project?
Occasional ContributorI changed the core type to soft controller and keep track of mem_reset_n generation.
dataout[0] from ARRIAV_DDIO_OUT - mem_reset_n
pll_addr_cmd_clk - exist
DATAINHI and DATAINLO - 2'b11
ARESET - 1'b0(from ~reset_reg[14])
Why???
Regular ContributorHi sir,
The signal tap tool cannot be used to get the signal from the mem_reset_n because the signal is the conduit between the memory and phy.
The signal tap can get the signal between user design and the memory controller.
In order to see the signal, you can do it by the simulation tool such Modelsim.
By simulation your design in the tool, you can trace the waveform of your signal.
By right you can see the interaction of the mem_reset_n signal.
Regards,
Adzim
Regular ContributorHi sir,
I hope you're doing great.
Do you still have further question on this case?
Regards,
Adzim
Occasional Contributorno, thx
Regular ContributorSetting the case to closure.
