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EBoln's avatar
EBoln
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

mem_reset_n always is low from DDR3 hard controller

Hi, i have ArriaV, DDR3 chips, but after deassert global and soft resets mem_reset_n stay is low. Soft reset generate after 1000 tick on 100MHz clk What else can affect this signal?
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi sir,


The signal tap tool cannot be used to get the signal from the mem_reset_n because the signal is the conduit between the memory and phy.

The signal tap can get the signal between user design and the memory controller.


In order to see the signal, you can do it by the simulation tool such Modelsim.

By simulation your design in the tool, you can trace the waveform of your signal.

By right you can see the interaction of the mem_reset_n signal.


Regards,

Adzim