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EBoln's avatar
EBoln
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

mem_reset_n always is low from DDR3 hard controller

Hi, i have ArriaV, DDR3 chips, but after deassert global and soft resets mem_reset_n stay is low. Soft reset generate after 1000 tick on 100MHz clk What else can affect this signal?
EBoln's avatar
EBoln
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

I changed the core type to soft controller and keep track of mem_reset_n generation.

dataout[0] from ARRIAV_DDIO_OUT - mem_reset_n

pll_addr_cmd_clk - exist

DATAINHI and DATAINLO - 2'b11

ARESET - 1'b0(from ~reset_reg[14])

Why???