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EBoln's avatar
EBoln
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

mem_reset_n always is low from DDR3 hard controller

Hi, i have ArriaV, DDR3 chips, but after deassert global and soft resets mem_reset_n stay is low. Soft reset generate after 1000 tick on 100MHz clk What else can affect this signal?
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Have you try to simulate your IP with the example design in your simulation?

EBoln's avatar
EBoln
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

At the moment, no, since there were no problems when using the core on Cyclone 5

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Can you give it a test?

    So before this you're working on Cyclone V device and it's worked.

    But now you try to implemented it in Arria V is it?

    Do you create a new IP for the Arria V or you use the existing project?

    • EBoln's avatar
      EBoln
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      I copy qsys file with DDR3 controller from CycloneV project to ArriaV project, ofcourse i change FPGA type in qsys file

    • EBoln's avatar
      EBoln
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      And i try create new qsys with controller

      • AdzimZM_Altera's avatar
        AdzimZM_Altera
        Icon for Regular Contributor rankRegular Contributor
        4 years ago

        Thanks for clarifying about your project.

        I guess there is no error during the IP generating process and compilation.

        But since you're facing some issue with the Arria V device, can you use the example design to simulate your IP in the Arria V?