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EBoln's avatar
EBoln
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

mem_reset_n always is low from DDR3 hard controller

Hi, i have ArriaV, DDR3 chips, but after deassert global and soft resets mem_reset_n stay is low. Soft reset generate after 1000 tick on 100MHz clk What else can affect this signal?
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Sir,

I'm Adzim. Thanks for using Intel Community.

According to the KDB here, it's looks like the global and soft resets can only trigger the mem_reset_n signal.

Are you using the example design in your simulation?

If not, can you simulate your IP with the example design?

Which Quartus software that you used?

Regards,

Adzim

  • EBoln's avatar
    EBoln
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago
    I am using 18.1.1 and 20.1 standard edition