Max 10 Jtag secure mode issues for lock/unlock jtag

Hi,

Per my understanding you are referring to design security. You can refer to AN 556 below for design security:

https://www.intel.com/content/www/us/en/docs/programmable/683269/current/verifying-jtag-secure-mode.html

Regards,

Aiman

Hi,
my first step would be to try the design example mentioned in the User Guide.

https://fpgacloud.intel.com/old_design_store/platform/15.0.0/Standard/max10-jtag-secure-unlock/

Unfortunately the Quartus 15.0 based example has been apparently deleted without substitution, respective knowledge base articles became useless. I wonder if there's any standard procedure at Intel to assure consistency of the knowledge base?

Regarding question 1, WYSIWYG atoms are low level primitives, not actually IP rather than a description of existing hardware. JTAG WYSIWYG atom fiftyfivenm_jtag is defined in fiftyfivenm_components.vhd

JTAG WYSIWYG Interface is HDL code in the example design, I presume.

AN556 quoted above isn't specifically dedicated to MAX10 but comes with a similar lock/unlock design example for Arria V. It can be probably adapted for MAX10 if the original user guide design example remains lost. See below the example design top.

Regards
Frank

Hi FvM,

Thanks for the response.

Is this link working?
https://fpgacloud.intel.com/old_design_store/platform/15.0.0/Standard/max10-jtag-secure-unlock/

For me it redirects to the design store. but didn't find any design related to JTAG secure unlock.

It would be great help if i can get short of design example or par if possible.

JTAG WYSIWYG Interface is HDL primitive. i tried and got it compiled. reviewing AN556 and arria v codes. but still proper connections is unclear.

About the connection somewhat i understand. so, actual jtag interface pins in/out of fpga should be directed with JTAG WYSIWYG atom?

Thanks in advance

what signals will be at my top design? will it be jtag signals? or WYSIWYG signals?

Hi,
the link is not working. Intel should either restore a link to the old design or update it.

The design is not connecting to actual JTAG pins, it uses internal JTAG nodes only.

do we need to enable this ip altera_soft_core_jtag_io or any other ip? or just user logic to be connected with this primitives.?

Hi,

There is actually new MAX 10 JTAG secure design example that is pending release to the FPGA design store as it require few approval.

I will check with engineering when this is expected to be published and the enhancements that were made (simulation example, HW validation). But I think it's in the best interest to wait for this newer design to be released.

For ip altera_soft_core_jtag_io, may i know where did you see this ip as it is not in the userguide.

https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/mega/mega_file_softcore_jtag_io.htm

Regards,

Aiman

Hi,

Amay here agiain I had an issue for logging in thus using different login ID thats ok , My main concern is that when exactly Intel is planning to launch example design for JTAG Security for MAX 10 FPGA Board , I guess MAX 10 FPGA seems to be not launched this year although quartus also has too many bugs which not solved or taken care by intel in new updates even PLL for MAX 10 FPGA output is not getting generated even if testbench is generated by tool itself and it an Global issue when i checked on multiple sites.

Please tell the exactly when intel is planning to drop example design for JTAG security , as you are suggesting to wait for new release as if MAX 10 FPGA is launched this year this seems to be Intel is list bother to take care or properly update quartus for best use , we as users understand that boards are not that costly that does not mean Intel should neglect this issues we face.

Till date some Megawizard without doing full screen does not take configuration also leading to quartus crash this was notified by Multiple users from quartus 15 this issue was seen till date the latest quartus has that issue what are the Intel Employee are working GOD KNOWS Franckly speaking if i continue to write one by one issues in quartus i may need a whole year , we as user are not working to find quartus Bugs we need FPGA to run our project for certain application.

Sometimes i feel Intel Employee take all FPGA Users for granted we are not getting paid to find Quartus bugs cuz of you irresponsibility we face issue and unnecessary lose time.

MY MAIN CONCERN IS JTAG SECURITY FOR MAX 10 I WANT EXACT DATE WHEN INTEL WILL LAUNCH EXAMPLE DESIGN FOR SAME DO NOT GIVE ME UNNECESSARY LINKS.

Regards,
AMAY

Hi Amay,

We sincerely apologize for the inconveniences that has occur. I manage to get the older design example after doing some digging. It was drop for some reason. I will provide that through forum email. Let me know if you did not received it.

Regards,

Aiman

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