Max 10 Jtag secure mode issues for lock/unlock jtag

Hi FvM,

Thanks for the response.

Is this link working?
https://fpgacloud.intel.com/old_design_store/platform/15.0.0/Standard/max10-jtag-secure-unlock/

For me it redirects to the design store. but didn't find any design related to JTAG secure unlock.

It would be great help if i can get short of design example or par if possible.

JTAG WYSIWYG Interface is HDL primitive. i tried and got it compiled. reviewing AN556 and arria v codes. but still proper connections is unclear.

About the connection somewhat i understand. so, actual jtag interface pins in/out of fpga should be directed with JTAG WYSIWYG atom?

Thanks in advance