Max 10 Jtag secure mode issues for lock/unlock jtag

Hi,
my first step would be to try the design example mentioned in the User Guide.

https://fpgacloud.intel.com/old_design_store/platform/15.0.0/Standard/max10-jtag-secure-unlock/

Unfortunately the Quartus 15.0 based example has been apparently deleted without substitution, respective knowledge base articles became useless. I wonder if there's any standard procedure at Intel to assure consistency of the knowledge base?

Regarding question 1, WYSIWYG atoms are low level primitives, not actually IP rather than a description of existing hardware. JTAG WYSIWYG atom fiftyfivenm_jtag is defined in fiftyfivenm_components.vhd

JTAG WYSIWYG Interface is HDL code in the example design, I presume.

AN556 quoted above isn't specifically dedicated to MAX10 but comes with a similar lock/unlock design example for Arria V. It can be probably adapted for MAX10 if the original user guide design example remains lost. See below the example design top.

Regards
Frank