Max 10 Jtag secure mode issues for lock/unlock jtag

Hi,

There is actually new MAX 10 JTAG secure design example that is pending release to the FPGA design store as it require few approval.

I will check with engineering when this is expected to be published and the enhancements that were made (simulation example, HW validation). But I think it's in the best interest to wait for this newer design to be released.

For ip altera_soft_core_jtag_io, may i know where did you see this ip as it is not in the userguide.

https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/mega/mega_file_softcore_jtag_io.htm

Regards,

Aiman