crazy_buddy1164New Contributor2 years agoMax 10 Jtag secure mode issues for lock/unlock jtag Hi All, I am reviewing the doc for MAX 10 JTAG Secure Mode. https://www.intel.com/content/www/us/en/docs/programmable/683865/current/fpga-configuration-overview.html page 58 with topic 3.9 I...Show More
Amay12New Contributor2 years agowhat signals will be at my top design? will it be jtag signals? or WYSIWYG signals?
Recent DiscussionsCyclone® 10 GX Avalon®-ST Interface for PCI Express example SimulationAgilex-7 AXI MCDMA for PCIe hangCan't generate F-Tile Ethernet Hard IP Design ExampleAvalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard ResetSolvedAgilex 7 slew rate reconfiguration