crazy_buddy1164New Contributor2 years agoMax 10 Jtag secure mode issues for lock/unlock jtag Hi All, I am reviewing the doc for MAX 10 JTAG Secure Mode. https://www.intel.com/content/www/us/en/docs/programmable/683865/current/fpga-configuration-overview.html page 58 with topic 3.9 I...Show More
Amay12New Contributor2 years agowhat signals will be at my top design? will it be jtag signals? or WYSIWYG signals?
Recent DiscussionsCascaded Avalon Stream Multiplexer in Platform Design does not forward valid data packetsCyclone V CAN triple samplingSolvedR_Tile PCIEAgilex 7 I F-Tile Direct PHY: example TB doesn't workSolvedWhy the Error Response Slave IP cannot work for Agilex 5 SOC FPGA?