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RamaMohan's avatar
RamaMohan
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7 years ago

Issue with PCIe HIP(A10) Gen3 model behavior in simulations with serial interface

Hi,

We are facing an issue in simualtions, with the data transmitted from PCIe hard-IP model during initialization while switching from Gen1 to Gen3 Speed. The model being used is the one for A10 FPGA device. Here’s the issue:

After moving Recovery.Speed state and sending TS ordered set, HIP is sending unknown symbols on Tx with HiZ on the lines.

The said behavior is seen repeatedly for a long time before HIP Tx enters electrical Idle.

The simulation has enabled fast_sims in serial mode.

Appreciate help/suggestions

Thanks,

RamaMohan

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