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RamaMohan's avatar
RamaMohan
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7 years ago

Issue with PCIe HIP(A10) Gen3 model behavior in simulations with serial interface

Hi, We are facing an issue in simualtions, with the data transmitted from PCIe hard-IP model during initialization while switching from Gen1 to Gen3 Speed. The model being used is the one for A10 F...
RamaMohan's avatar
RamaMohan
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hi Nathan,

Sorry for the confusion. We are not using Intel BFMs in the bench. We are only using Intel PCIe HIP DUT ​ and all the bench are not from intel. We di go through the section referred by you in userguide regarding equalization and we are in sync with you.

  1. We came across this equalization issue where RC model is initiating Phase2, 3 equalization but DUT(which is Intel PCIe HIP) is stuck at phase3. And when we skipped the phase3 equalization step LTSSM went to L0 state. But, note we did all this EP monitor disabled. But for successful operation we need the Monitor as well in bench.
  2. The reason for EP monitor not working is HiZ being sent by DUT Tx which is a spec violation

We did the changes suggested by you to the IP and ran simulations. Still we see the same issue.

Were you reproduce the issue at your end with the IP files provided by me?

Thanks,

RamaMohan