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RamaMohan's avatar
RamaMohan
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Issue with PCIe HIP(A10) Gen3 model behavior in simulations with serial interface

Hi, We are facing an issue in simualtions, with the data transmitted from PCIe hard-IP model during initialization while switching from Gen1 to Gen3 Speed. The model being used is the one for A10 F...
Nathan_R_Intel's avatar
Nathan_R_Intel
Icon for Contributor rankContributor
7 years ago

Hie RamaMohan,

Well as long as you use the AVST-SRIOV Interface (regardless if SR-IOV is enabled), the Intel-BFM don't support Gen3 Phase 2 and Phase 3 equalization. This is covered in our user guide (section 10.5.4).

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_sriov.pdf

For the SRIOV interface, the root port BFM (used for simulation) does not support Phase 2 and Phase 3 of Gen3 equalization. Hence, to achieve Gen3, the LTSSM will move to Recovery.Speed after speed change is requested. At this point, the root port BFM in simulation does not perform equalization and return RcvrLock. Hence, LTSSM cannot move beyond this.

Hence using Intel BFM as your root port in simulation will cause this behavior. i just checked this issue even exist in AVMM-DMA interface.

Hence, to workaround this issue, you will need to use a third party BFM as root port.

Regards,

Nathan