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RamaMohan's avatar
RamaMohan
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Issue with PCIe HIP(A10) Gen3 model behavior in simulations with serial interface

Hi, We are facing an issue in simualtions, with the data transmitted from PCIe hard-IP model during initialization while switching from Gen1 to Gen3 Speed. The model being used is the one for A10 F...
Nathan_R_Intel's avatar
Nathan_R_Intel
Icon for Contributor rankContributor
7 years ago

Hie RamaMohan,

The files you have attached only contains the pcie_ep_x8.ip file. This will take some effort on my side to regenerate all the simulation files, find a root port BFM from a third party, create a top level and simulation script that can show the failure. Could you help provide zip all the EP library files and the root port library files so, I could reproduce the simulation issue on my sides. If you are unable to due to proprietary reasons, then you will need to allow me sometime to reproduce on my side.

Regards,

Nathan