Forum Discussion
Issue with PCIe HIP(A10) Gen3 model behavior in simulations with serial interface
Hi,
We are facing an issue in simualtions, with the data transmitted from PCIe hard-IP model during initialization while switching from Gen1 to Gen3 Speed. The model being used is the one for A10 FPGA device. Here’s the issue:
After moving Recovery.Speed state and sending TS ordered set, HIP is sending unknown symbols on Tx with HiZ on the lines.
The said behavior is seen repeatedly for a long time before HIP Tx enters electrical Idle.
The simulation has enabled fast_sims in serial mode.
Appreciate help/suggestions
Thanks,
RamaMohan
22 Replies
- RamaMohan
Occasional Contributor
Hi Nathan,
We have both the configurations with SRIOV enabled and without SRIOV enabled as we need 2 endpoints. I've attached the IP config files of the both the EPs.
We are seeing the same issue for both the endpoints. We are using the sriov sim files except for all the unique modules specific to non-sriov config.
But, I'm wondering how SRIOV would impact the LTSSM behavior in your BFM.
Thanks,
RamaMohan
- Nathan_R_Intel
Contributor
Hie RamaMohan,
Well as long as you use the AVST-SRIOV Interface (regardless if SR-IOV is enabled), the Intel-BFM don't support Gen3 Phase 2 and Phase 3 equalization. This is covered in our user guide (section 10.5.4).
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_sriov.pdf
For the SRIOV interface, the root port BFM (used for simulation) does not support Phase 2 and Phase 3 of Gen3 equalization. Hence, to achieve Gen3, the LTSSM will move to Recovery.Speed after speed change is requested. At this point, the root port BFM in simulation does not perform equalization and return RcvrLock. Hence, LTSSM cannot move beyond this.
Hence using Intel BFM as your root port in simulation will cause this behavior. i just checked this issue even exist in AVMM-DMA interface.
Hence, to workaround this issue, you will need to use a third party BFM as root port.
Regards,
Nathan
- RamaMohan
Occasional Contributor
Hi Nathan,
Sorry for the confusion. We are not using Intel BFMs in the bench. We are only using Intel PCIe HIP DUT and all the bench are not from intel. We di go through the section referred by you in userguide regarding equalization and we are in sync with you.
- We came across this equalization issue where RC model is initiating Phase2, 3 equalization but DUT(which is Intel PCIe HIP) is stuck at phase3. And when we skipped the phase3 equalization step LTSSM went to L0 state. But, note we did all this EP monitor disabled. But for successful operation we need the Monitor as well in bench.
- The reason for EP monitor not working is HiZ being sent by DUT Tx which is a spec violation
We did the changes suggested by you to the IP and ran simulations. Still we see the same issue.
Were you reproduce the issue at your end with the IP files provided by me?
Thanks,
RamaMohan
- Nathan_R_Intel
Contributor
Hie RamaMohan,
The files you have attached only contains the pcie_ep_x8.ip file. This will take some effort on my side to regenerate all the simulation files, find a root port BFM from a third party, create a top level and simulation script that can show the failure. Could you help provide zip all the EP library files and the root port library files so, I could reproduce the simulation issue on my sides. If you are unable to due to proprietary reasons, then you will need to allow me sometime to reproduce on my side.
Regards,
Nathan
- RamaMohan
Occasional Contributor
Hi Nathan,
I don't think I will be able to share Root Port BFM now. I think generating EP library from .ip file is simple. Isn't it. We are using 17.1 version of Quartus Prime and target device is 10AX115N3F40E2SG.
Let me know if you still want to send you EP library files.
Thanks,
RamaMohan
- Nathan_R_Intel
Contributor
Hie RamaMohan,
Yes it is not difficult to generate the End Point library files from .ip files; but wanted to check the exact library files. Even similar Quartus versions with patch or updates could have different library files.
Anyway, I will need to update my available BFM to be Gen3 capable and attempt to replicate this issue on myside.
I will be out from 7th to 13th December. Hence, please expect my next response only after 14th December 2018.
I will need the following information from you.
i. Have you installed any patch or update to Quartus Prime 17.1
ii. Which tool are you using for simulation
Regards,
Nathan
- RamaMohan
Occasional Contributor
Hi Nathan, We are currently using below version of Quartus. Simulation tool being used is vcs (Version O-2018.09) Thanks, RamaMohan - RamaMohan
Occasional Contributor
Here's the quartus version: 17.1.0 Build 240 10/25/2017 SJ Pro Edition
Thanks,
RamaMohan
- RamaMohan
Occasional Contributor
Hi Nathan,
Can you please update on this issue. Our PCIe Gen3 progress is currently blocked because of this issue.
Thanks,
RamaMohan
- Nathan_R_Intel
Contributor
Hie RamaMohan,
I was unable to duplicate the issue yet on myside using Modelsim. I will be trying with VCS and updating you by tomorrow.
Regards,
Nathan