Interfacing the DSP IP cores with Nios ii processor using Avalon-ST

I have successfully built a microphone signal filter using the CIC and FIR DSP IP cores, and now I want to store the output of the FIR filter to a Nios ii processor's main memory. I'm doing this in order to further read the output from multiple microphones from the main memory and then send them using the triple speed Ethernet IP. To do this, I tried to use the SGDMA IP core in Stream to Memory mode, which is supposed to store data from an Avalon-ST source to memory. However, the Avalon-ST interface of the FIR core's output and the SGDMA IP core's input are not compatible. The bits_per_symbol parameter for the FIR core varies with its output data width and cannot be set manually, while the bits_per_symbol parameter for the SGDMA core is fixed to 8. In addition, the SGDMA core requires packet transmission while the FIR core does not support that. The output width of my FIR filter is 16 bits and I want to change its output format to: 8 bits per symbol, 2 symbols per beat, and with packet support. Is there a convenient way to achieve my goal so that I can make the two Avalon-ST interface compatible? I am using Quartus Prime Standard 19.1 and I develop the system on an Arria V FPGA. Thanks.