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yt_liu's avatar
yt_liu
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Interfacing the DSP IP cores with Nios ii processor using Avalon-ST

I have successfully built a microphone signal filter using the CIC and FIR DSP IP cores, and now I want to store the output of the FIR filter to a Nios ii processor's main memory. I'm doing this in o...
  • CheepinC_altera's avatar
    CheepinC_altera
    5 years ago

    Hi,


    Thanks for your update. Sorry as I am not really a design expert and could not really comment on the right memory IP to use. However, depending on the size of memory required, you can explore into normal FIFO, on-chip memory ie ROM/RAM and also DDR IP. Note that you would still need to create some glue logic to perform the conversion on your own.

    Please let me know if there is any concern. Thank you.



    Best regards,

    Chee Pin


CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


As I understand it, you are trying to interface between the FIR IP and the SDGMA core directly. Sorry as I am not aware of direct way for this. Probably you might need to look into storing the FIR output into some memory and then create some logic to convert it into SDGMA compatible format.


Please let me know if there is any concern. Thank you.


Best regards,

Chee Pin


  • yt_liu's avatar
    yt_liu
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi Chee Pin, your understanding is exactly correct! Thanks for the information. Do you have any suggestions on what memory IP core I should use in order to both store the data from the FIR IP to it and provide a Avalon-MM interface (I guess?) for the SGDMA module? Thanks.