intel_rtile_cxl_top_cxltyp3_ed with out of order support (ooo enabled) Timing issues (23.2)

Attaching the design results report (renamed from .rpt to log).

Hi @brian1211
Is this related to https://community.intel.com/t5/FPGA-Intellectual-Property/CXL-type-3-design-example-Design-Assistant-Errors/m-p/1502466#M27791

These DRC Checks were enabled late in 22.4 onwards. These errors are expected for 23.1 and expected to be fixed by 23.3. DRC violations are not impacting the functionality so far.

Hi @JonWay_C_Intel ,

Not worried about the DRC checks, it's the 700+ timing constraints from the various *.sdc files that aren't being used that I have issue with. They are below the DRC checks you mention that have been around for a while, the ones below (#7-9):

TMC-20023 - Invalid Set Net Delay Assignment
TMC-20025 - Ignored or Overridden Constraints
TMC-20026 - Empty Collection Due To Unmatched Filter

Are the new ones that are concerning.

Thanks for the elaboration. Let me check and get back to you.