ContributionsMost RecentMost LikesSolutionsRe: Cyclone V SX-GX connection SGMII requires a line rate of 1.25 Gbps, which means it must utilize the FPGA's transceiver (XCVR) channels. However, the 5CSXFC6D6 device only provides 9 transceiver channels, while you're aiming to implement 10 SGMII interfaces—each needing a dedicated channel. This creates a shortfall of one transceiver channel for your intended design. Re: USB3.x LFPS transmission and detection with FPGA transceiver Based on this published paper, the concept should be similar wrt to LFPS implementation using FPGA https://arxiv.org/pdf/2301.11505v1 1. LFPS Reception: Does the FPGA transceiver provide any signal to indicate electrical idle state? Altera FPGA transceivers do provide a signal that can be used to detect the presence or absence of electrical idle. Specifically: See: https://community.intel.com/t5/FPGA-Wiki/Design-Example-PHY-Interface-for-PCI-Express-PIPE/ta-p/735980 The pipe_rxelecidle signal (or its equivalent depending on the PIPE interface implementation) indicates whether the receiver is in an electrical idle state. When RXELECIDLE = 0, it implies that LFPS is being received (i.e., the link is active). When RXELECIDLE = 1, it indicates that the link is in electrical idle, and no LFPS is being received. This behavior is consistent with USB 3.x PHY expectations, where LFPS detection relies on transitions between idle and active states on the differential lines1. 2. LFPS Transmission: Can LFPS be sent by controlling pipe_txdetectrx and pipe_txelecidle? Theorectically, LFPS transmission can be achieved by manipulating the transceiver's PIPE interface signals: To initiate LFPS transmission, the following conditions are typically used: TXDETECTRX = 1 TXELECIDLE = 1 txpd = 2'b00 and rxpd = 2'b00 (power-down controls) To wake up a link partner, the conditions change to: TXELECIDLE = 0 txppd = 2'b01 and rxpd = 2'b01 These control signals directly influence the raw data output of the SerDes block, allowing you to generate LFPS bursts by toggling the differential lines at low frequencies (typically 10–50 MHz square waves)1. Additionally, LFPS generation can be done in soft logic by bypassing 8b10b encoding and directly driving the transceiver with patterns like 0xFFFFFFFFFF to simulate high-level signals. Timing must be carefully managed to meet USB 3.x LFPS specifications (e.g., tBurst, tPeriod, tRepeat) Re: Agilex 5 100G Ethernet realization There is definitely no single channel 100G in Agilex 5. So I guess you are referring to something like 4 x25G. This is also not viable. If you refer here: 1.5. Agilex® 5 Ethernet Hard IP Features The most you have is 25-1. Re: where can find the PAC N3000 software package "n3000_ias_1_1_pv_rte_installer.tar.gz" ? Good news! Both the CentOS and RHEL packages were re-uploaded to the same link as before i.e. Intel® FPGA PAC N3000 Acceleration Stacks v1.3.1 And, to re-emphasize, N3000 is discontinued and there is no update to the package nor support available. Re: where can find the PAC N3000 software package "n3000_ias_1_1_pv_rte_installer.tar.gz" ? Your voices are heard! I have filed to the internal team, and let the decision-makers reconsider putting the package into the web. Note that the N3000 is discontinued, even if the package were to be re-uploaded, there is no update to the package nor support available. Re: where can find the PAC N3000 software package "n3000_ias_1_1_pv_rte_installer.tar.gz" ? It seems Intel is discontinuing the Intel® FPGA Programmable Acceleration Card N3000. Please read product discontinuance notification PDN2211 for more information, which led to the removal of the packages. May I know what is the effort is ongoing with the N3000? Re: where can find the PAC N3000 software package "n3000_ias_1_1_pv_rte_installer.tar.gz" ? The Centos RTE works for me... The RHEL RTE leads to "Not Found" <---- is this what you are referring to? Re: where can find the PAC N3000 software package "n3000_ias_1_1_pv_rte_installer.tar.gz" ? It is still here: https://www.intel.com/content/www/us/en/software-kit/665770/intel-fpga-pac-n3000-acceleration-stacks-v1-3-1.html Re: quartus_pgm: Programming option E is illegal OK, im helping out anyone who is facing the same problem who was sure they had the correct CLI command. If you are getting the error as below. Error (213008): Programming option string "“ei" is illegal. Refer to --help for legal programming option formats. Example: quartus_pgm -c 2 -m jtag -o "ei;device_info.txt;AGFC023R25A" --dev_info TYPE every character (DO NOT COPY PASTE from document) into the terminal. It seems the terminal interpret the special character differently for the type-in vs copy/paste. Re: intel_type3_cxl_ip_0_ed with OOO support only supports 125 pending read IDs? i have sent you a personal message