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brian1211's avatar
brian1211
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
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intel_rtile_cxl_top_cxltyp3_ed with out of order support (ooo enabled) Timing issues (23.2)

In building the intel_rtile_cxl_top_cxltyp3_ed with the ooo enabled we get some design assistant failures around the timing, of concern are these: TMC-20023 - Invalid Set Net Delay Assignment TMC-2...
Cxl
  • JonWay_C_Intel's avatar
    JonWay_C_Intel
    3 years ago

    I have checked with the internal team. These DRC messages are expected. The engineering team is still working on cleaning up the sdc constraints in 23.3. The DRC violations should not impact timing, and not cause any functionality problem.

JonWay_C_Intel's avatar
JonWay_C_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

I have checked with the internal team. These DRC messages are expected. The engineering team is still working on cleaning up the sdc constraints in 23.3. The DRC violations should not impact timing, and not cause any functionality problem.