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JonWay_C_Intel
Frequent Contributor
3 years agoHi @brian1211
Is this related to https://community.intel.com/t5/FPGA-Intellectual-Property/CXL-type-3-design-example-Design-Assistant-Errors/m-p/1502466#M27791
These DRC Checks were enabled late in 22.4 onwards. These errors are expected for 23.1 and expected to be fixed by 23.3. DRC violations are not impacting the functionality so far.