Forum Discussion
brian1211
Occasional Contributor
Occasional Contributorintel_rtile_cxl_top_cxltyp3_ed with out of order support (ooo enabled) Timing issues (23.2)
In building the intel_rtile_cxl_top_cxltyp3_ed with the ooo enabled we get some design assistant failures around the timing, of concern are these: TMC-20023 - Invalid Set Net Delay Assignment TMC-2...
I have checked with the internal team. These DRC messages are expected. The engineering team is still working on cleaning up the sdc constraints in 23.3. The DRC violations should not impact timing, and not cause any functionality problem.
JonWay_altera
Frequent Contributor
Frequent ContributorHi @brian1211
Is this related to https://community.intel.com/t5/FPGA-Intellectual-Property/CXL-type-3-design-example-Design-Assistant-Errors/m-p/1502466#M27791
These DRC Checks were enabled late in 22.4 onwards. These errors are expected for 23.1 and expected to be fixed by 23.3. DRC violations are not impacting the functionality so far.
