how to generate verilog file from dsp builder

Question

please tell me how can i generate verilog file from dsp builder..i don't want vhdl file..

altera_forum · Answer

DSP Builder only generates VHDL. if you're looking to simulate you might try finding instructions for simgen, which are lurking on Altera's website. simgen can create a Verilog simulation model for VHDL files.

altera_forum · Answer

sorry sir..but i didn't get your meaning of simgen..what is simgen?? i didn't get any result regarding it on altera site

altera_forum · Answer

this was my 3rd hit for simgen:  http://www.altera.com/support/kdb/solutions/rd07132006_347.html

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how to generate verilog file from dsp builder

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