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Altera_Forum
Honored Contributor
Honored Contributorhow to generate verilog file from dsp builder
please tell me how can i generate verilog file from dsp builder..i don't want vhdl file..
Altera_ForumHonored Contributor
Honored Contributorsorry sir..but i didn't get your meaning of simgen..what is simgen?? i didn't get any result regarding it on altera site
