Altera_Forum
Honored Contributor
Honored Contributorhow to generate verilog file from dsp builder
please tell me how can i generate verilog file from dsp builder..i don't want vhdl file..
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Altera_ForumHonored Contributor
Honored ContributorDSP Builder only generates VHDL. if you're looking to simulate you might try finding instructions for simgen, which are lurking on Altera's website. simgen can create a Verilog simulation model for VHDL files.
