Altera_Forum
Honored Contributor
Honored Contributorhow to generate verilog file from dsp builder
please tell me how can i generate verilog file from dsp builder..i don't want vhdl file..
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Altera_ForumHonored Contributor
Honored Contributorthis was my 3rd hit for simgen:
http://www.altera.com/support/kdb/solutions/rd07132006_347.html
