How can I mux an AvalonMM Bus (VIP_VFR -> 2x SDRAM)

Is there a reason why you cannot just connect the frame reader directly to both SDRAM modules?

When you want to switch between them, you can reset the base address the frame reader uses via it's slave port.

I agree with Kevin. Any reason why you can't just connect the master to both memories? If not, a switch would be really easy to make. You just need to make sure it's got all the same required signals and you're set.

Jake

Hello and thanks for your replies.

I want to switch without the slave port, because I got timing problems while switching with it. To explain that: I am not just switching the FrameReader, I simultanious switch a selfwritten module, that creates the frame in sdram. So I will have to switch the two modules at the exact same moment. Also I will get more things to consider that way. For example I will have to monitor for the FrameReader to finish befopre I can switch that way. I am not using any C-Code, I am configurating the FrameReader from another VHDL-Module with Avalon-Bus at the moment. So Kevins idea would be some kind of troublesome I believe.

@jakobjones: Unfortunately that switch is not that easy to made. I have already programmed a switch to switch my selfwritten module. There I can just connect all wires I require and switch them like in my first sketch. As I tried to explain, for the FrameReader this does not work just to connect every required wire, because the SOPC-Builder seems to recognise when a module needs piplined/burst capabilities. I got stuck in the programming of this switch many times now. The error I get from SOPC-Builder says: "Slave with readdatavalid signal must support at least 1 pending read" Can you suggest/explain what I have to implement, to achieve pending read support in the module? Perhaps this seams like an easy problem to you, but I don't get it.

I have also attached another sketch to make the problem a bit clearer (I hope it gets clearer from that). The design is inspired by the FrameBuffer.

Thanks in advance.

Ok, that was really absolutely annoying right now!!

I just found the problem after some days of programming. Even if you implement the readdatavalid signal you must insert a number > 0 for max pending read transactions in the setup-dialog from SOPC-Builder while creating the custom module. I had not changed this and so he wrote 0 in the tcl file and created the error message I got the whole time. Perhaps my first module worked all the time, but I searched at the totally wrong place for the error.

*GrmBL!!!!*@#! :rolleyes:

Ok, I am now again working on this problem and I did not get it to work. Can you please help me again?!

I followed Kevins advise and I am now trying to access the SDRAM by the addresses.

SDRAM_0: 0x000000000 to 0x07fffffff

SDRAM_1: 0x080000000 to 0x0ffffffff

My selfwritten module is connected to both Rams. I have got a 32Bit address std_logic_vector. How can I now access one time the SDRAM_0 and one time the SDRAM_1? Everytime I try to access I only get the data from SDRAM_0. Is there some kind of trick with this? In my opinion the Address Decode Logic wants to fool me, but I did not find the right key to get it properly working.

Thanks for any advise.

Accessing the two different SDRAMs should be as simple as using the correct address.

Are you absolutely sure you are using the correct address? The Avalon bus uses word addresses, not byte addresses. For example, assuming a 32 bit data width, you would set the address to 0x020000000 to access the first word of SDRAM_1.

Thanks for your reply Kevin. I am now again sitting at this SOPC-System since two hours and don't get it.

Here is a description, what I think I have to do, perhaps you can tell from it where my fault is.

I have attached a screenshot of my SOPC-System to this thread. It shows two sdram_writer components, that write different testpattern into the SDRAM_0 and SDRAM_1. I am configurating the FrameReader from within a VHDL-Module by writing to it's registers.

So to address SDRAM_0 from my module I should use:

Address in SOPC / Avalon Access

0x00000000 / 0x00000000

0x00000001 / 0x00000004

0x00000002 / 0x00000008

0x00000003 / 0x0000000c

...

To access SDRAM_1 I add the baseadress as offset:

Address in SOPC / Avalon Access

0x08000000 / 0x02000000

0x08000001 / 0x02000004

0x08000002 / 0x02000008

0x08000003 / 0x0200000c

...

To get to the right addresses in my modules I write like:

address <= write_address_counter(29 downto 0) & "00";

This gives:

address <= "000000000000000000000000000000" & "00"; -- 0

address <= "000000000000000000000000000001" & "00"; -- 4

address <= "000000000000000000000000000010" & "00"; -- 8

address <= "000000000000000000000000000011" & "00"; -- c

...

From your reply I would think this is the right adressing. Where I am unsure is the adressing from my modules that generate the testpatterns.

When I have connected an Avalon-Memorymapped Master to only one MM-Slave I would think, that I will not have to address using an offset, because the adress decode will throw away that parts of the address, it does not use to address the component. Is this right?

Thanks for any help.

I got it now working, but I could not explain to myself, why it only works like this.

The problem was in the initialisation of my FrameWriter. As it is written in the VIP Suite Guide A-25 where the Control Register Map of the FrameReader can be found, the Frame 0 Base Address schould be given as 32-bit base address. So here we don't have the Byte Addressing. I tried to pass "00001000000000000000000000000000" as data to the FrameReader, but this does not work. When I now tried to pass over the value as hexadecimal, it works.

Don't work:

writedata <= "00001000000000000000000000000000";

Works:

writedata <= x"08000000";

(where writedate is out std_logic_vector(31 downto 0))

I don't get it, in my opinion this is the same? x"08000000" = 134217728 = 2^27 = "00001000000000000000000000000000" I calculated it on paper again.

Thanks for your help Kevin!

Your post is very usful. I face a problem in my design, I use the frame reader in my design with the following settings:

Bits per pixel per color plane: 8

Number of color planes in parallel: 3

Number of color planes in sequence: 1

Maximum Image width: 1920

Maximum Image height: 1080

Master port width: 64

Read master FIFO depth: 1024

Read master FIFO burst target: 64

Use separate clock for the Avalon MM master interface: unchecked

Kindly confirm if the following calculations for number the words and the Single Cycle Color Patterns are true or not

1- // Words

IOWR(FRAMEREADER_BASE, 5, 259200); // (1920*1080*8*3)/48= 1036800

2- // Single Cycle Color Patterns

IOWR(FRAMEREADER_BASE, 6, 2073600); // 1920*1080=2073600 number of pixels in the frame

I apreciate your reply ASAP