How can I mux an AvalonMM Bus (VIP_VFR -> 2x SDRAM)

Thanks for your reply Kevin. I am now again sitting at this SOPC-System since two hours and don't get it.

Here is a description, what I think I have to do, perhaps you can tell from it where my fault is.

I have attached a screenshot of my SOPC-System to this thread. It shows two sdram_writer components, that write different testpattern into the SDRAM_0 and SDRAM_1. I am configurating the FrameReader from within a VHDL-Module by writing to it's registers.

So to address SDRAM_0 from my module I should use:

Address in SOPC / Avalon Access

0x00000000 / 0x00000000

0x00000001 / 0x00000004

0x00000002 / 0x00000008

0x00000003 / 0x0000000c

...

To access SDRAM_1 I add the baseadress as offset:

Address in SOPC / Avalon Access

0x08000000 / 0x02000000

0x08000001 / 0x02000004

0x08000002 / 0x02000008

0x08000003 / 0x0200000c

...

To get to the right addresses in my modules I write like:

address <= write_address_counter(29 downto 0) & "00";

This gives:

address <= "000000000000000000000000000000" & "00"; -- 0

address <= "000000000000000000000000000001" & "00"; -- 4

address <= "000000000000000000000000000010" & "00"; -- 8

address <= "000000000000000000000000000011" & "00"; -- c

...

From your reply I would think this is the right adressing. Where I am unsure is the adressing from my modules that generate the testpatterns.

When I have connected an Avalon-Memorymapped Master to only one MM-Slave I would think, that I will not have to address using an offset, because the adress decode will throw away that parts of the address, it does not use to address the component. Is this right?

Thanks for any help.