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DdeBr's avatar
DdeBr
Icon for New Contributor rankNew Contributor
6 years ago

How can I configure the chip select high time (time between flash operations) when using the Generic Serial Flash Interface IP

We are clocking the Generic Serial Flash Interface IP at 156.25 MHz on a Cyclone-10GX, with a clock divider of 4. We can configure the chip select delay before the first clock, and after the last clock, but the chip select high time between commands is too short for our flash.

Our SPI Flash requires a minimum of 6 ns between read operations, and a minimum of 30 ns between program or erase operations.

Using SignalTap, this appears to be two cycles with the IP so 12.5 ns. Read operations are successful, but the when writing, the status poll is perceived as part of the program operation, because the SPI flash misses the chip select going high.

Is there a way to configure how long the chip select stays high after a program or erase command?

11 Replies

    • DdeBr's avatar
      DdeBr
      Icon for New Contributor rankNew Contributor
      6 years ago

      I'm sorry but as far as I can see the chip select delay is only configurable between the chip select assertion and the first clock and between the last clock and chip select de-assert. Both from signal tap and by inspecting the generated code, it looks like the time between operations is always two clock cycles. We have been unsuccessful in changing this with these register settings.

      We are using this IP with several flashes

      • Winbond W25Q32JW (requires 50 ns between programming operations)
      • Micron MT25QU02GCBB (requires 30 ns between operations)
      • Micron MT25QU256ABA

      The only solution that seems to work for us is reducing the input clock to the IP to make sure the two clock cycle inactive time is long enough. This again means that the maximum QSPI clock frequency we can use is 19.5 MHz, which quite unfortunate when reading works at 78 MHz.

  • JohnT_Altera's avatar
    JohnT_Altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    For Micron MT25Q, you can stll used the Serial Flash Controller Interface IP which we have verified. In order to enable it you may refer to https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2018/how-do-i-enable-micron-s-mt25q-support-for-eol-of-epcq---256mb--.html. For Winbond flash, the only solution is to use Generic Serial Flash Interface.

    May I know if you are facing issue during read? If yes, you can still modify the read delay.

  • nlete's avatar
    nlete
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    I'am facing the same problem.

    I use the Generic Serial Flash Interface IP to access an EPCQ256 flash. The internal clock provided to the IP is 100MHz.

    The IP does not respect the timing characteristic of the EPCQ256 for the chip select high time (Tcsh = 50ns min in the datasheet). I checked with a scope, and the chip select high time is 20ns.

    Fortunately, it works for the read and write operations, but it failed for the sector erase or chip erase operation.

    The best way to solve this issue would be to add a parameter in order to configure this chip select high time.

  • JohnT_Altera's avatar
    JohnT_Altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    May I know what is the setting used in the IP and which FPGA device are you using?

  • nlete's avatar
    nlete
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    The FPGA is a Cyclone V (5CGXBC4C6F27C7N)

    The IP setting:

    @0: 0x00101

    @1: 0x00004

    @2: 0x00088

    @3: 0x00000

    @4: 0x22220

    @5: 0x00AEB

    @6: 0x00512

  • JohnT_Altera's avatar
    JohnT_Altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Could you try below setting?

    @1: 0x00010

    @2: 0x00000

    @3: 0x00000

    @4: 0x00000

    @5: 0x00403

    @6: 0x00502

  • nlete's avatar
    nlete
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi John,

    I tried with your settings, and it does not work. (error in read values, write operations not working)

    With your settings, the chip select high time is 30ns and does not respect the EPCQ256 datasheet (50 ns min).

    I think it is only a question of chip select high time. I increased the time between two commands sent to the IP in order to increase the CS high time, and it works for all commands (sector erase, chip erase...).

  • JohnT_Altera's avatar
    JohnT_Altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Are you saying, that everything work fine with the below setting? If yes, then can you use the setting to move forward?

    @1: 0x00010

    @2: 0x00088

    @3: 0x00000

    @4: 0x00000

    @5: 0x00403

    @6: 0x00502

    • JohnT_Altera's avatar
      JohnT_Altera
      Icon for Regular Contributor rankRegular Contributor
      6 years ago

      Hi,

      May I know if this setting help on your issue?