Forum Discussion
DdeBr
New Contributor
6 years agoHow can I configure the chip select high time (time between flash operations) when using the Generic Serial Flash Interface IP
We are clocking the Generic Serial Flash Interface IP at 156.25 MHz on a Cyclone-10GX, with a clock divider of 4. We can configure the chip select delay before the first clock, and after the last clo...
JohnT_Altera
Regular Contributor
6 years agoHi,
May I know what is the setting used in the IP and which FPGA device are you using?