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DdeBr's avatar
DdeBr
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6 years ago

How can I configure the chip select high time (time between flash operations) when using the Generic Serial Flash Interface IP

We are clocking the Generic Serial Flash Interface IP at 156.25 MHz on a Cyclone-10GX, with a clock divider of 4. We can configure the chip select delay before the first clock, and after the last clo...
  • DdeBr's avatar
    DdeBr
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    5 years ago

    I'm sorry but as far as I can see the chip select delay is only configurable between the chip select assertion and the first clock and between the last clock and chip select de-assert. Both from signal tap and by inspecting the generated code, it looks like the time between operations is always two clock cycles. We have been unsuccessful in changing this with these register settings.

    We are using this IP with several flashes

    • Winbond W25Q32JW (requires 50 ns between programming operations)
    • Micron MT25QU02GCBB (requires 30 ns between operations)
    • Micron MT25QU256ABA

    The only solution that seems to work for us is reducing the input clock to the IP to make sure the two clock cycle inactive time is long enough. This again means that the maximum QSPI clock frequency we can use is 19.5 MHz, which quite unfortunate when reading works at 78 MHz.