Contributor[HDMI IP] info_avi[112] control bit is assigned to Virtual Pin -> why?
Hi All,
According to the HDMI Intel® FPGA IP User Guide (Table 24), the info_avi[112] is the control bit, which define whether the HDMI Core insert/filter packets on the Auxiliary Data Port.
But, in the HDMI Example Design, the info_avi[112] is connected to the ~user_pb_2 signal, which is defined as a virtual pin:
Here is from file c10_hdmi2_demo.v, line 512:
.info_avi ({~user_pb_2, tx_info_avi}),
Here is from the c10_hdmi2_demo.qsf (user_pb_2 is assigned to user_pb[2] in another file):
set_instance_assignment -name VIRTUAL_PIN ON -to user_pb[2]
So, how should this work? Why is the info_avi[112] control bit assigned to a Virtual Pin?
Thank you!
Hi amildm,
Good day.
>Will the infoframe packet be sent out when info_avi[112]=1and blocked/filtered out when info_avi[112]=0?
I believe the above statement is incorrect.
Based on the Cyclone 10GX schematic file:
C10gx Schematic file
and the HDMI IP User Guide:
HDMI IP User Guide
when info_avi=1, it will not insert the Infoframe.
With that, the Infoframe packet will be sent out when info_avi[112]=0 (user_pb_2=1, released) and blocked/filtered out when info_avi[112]=1 (user_pb_2=0, pressed) .
Hope this answer your question.
Thank you.
Best Regards,
ZulsyafiqH_Intel
