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amildm's avatar
amildm
Icon for Contributor rankContributor
4 years ago
Solved

[HDMI IP] info_avi[112] control bit is assigned to Virtual Pin -> why?

Hi All, According to the HDMI Intel® FPGA IP User Guide (Table 24), the info_avi[112] is the control bit, which define whether the HDMI Core insert/filter packets on the Auxiliary Data Port. h...
  • ZH_Intel's avatar
    ZH_Intel
    4 years ago

    Hi amildm,

    Good day.

    >Will the infoframe packet be sent out when info_avi[112]=1and blocked/filtered out when info_avi[112]=0?

    I believe the above statement is incorrect.

    Based on the Cyclone 10GX schematic file:

    C10gx Schematic file

    and the HDMI IP User Guide:

    HDMI IP User Guide

    when info_avi=1, it will not insert the Infoframe.

    With that, the Infoframe packet will be sent out when info_avi[112]=0 (user_pb_2=1, released) and blocked/filtered out when info_avi[112]=1 (user_pb_2=0, pressed) .

    Hope this answer your question.

    Thank you.

    Best Regards,

    ZulsyafiqH_Intel

ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
4 years ago

Hi amildm,

Thank you for reaching out.

Yes, you are correct, the info_avi[112] is the control bit.

After checking from my side, from file c10_hdmi2_demo.v, line 481:

.info_avi ({~user_pb_2, tx_info_avi}),

From file c10_hdmi2_demo.qsf, the info_avi[112] control bit assigned to pin AH2.

.qsf

May I know your Quartus software version?

Thank you.

Best Regards,

ZulsyafiqH_Intel