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amildm's avatar
amildm
Icon for Contributor rankContributor
4 years ago
Solved

[HDMI IP] info_avi[112] control bit is assigned to Virtual Pin -> why?

Hi All, According to the HDMI Intel® FPGA IP User Guide (Table 24), the info_avi[112] is the control bit, which define whether the HDMI Core insert/filter packets on the Auxiliary Data Port. h...
  • ZH_Intel's avatar
    ZH_Intel
    4 years ago

    Hi amildm,

    Good day.

    >Will the infoframe packet be sent out when info_avi[112]=1and blocked/filtered out when info_avi[112]=0?

    I believe the above statement is incorrect.

    Based on the Cyclone 10GX schematic file:

    C10gx Schematic file

    and the HDMI IP User Guide:

    HDMI IP User Guide

    when info_avi=1, it will not insert the Infoframe.

    With that, the Infoframe packet will be sent out when info_avi[112]=0 (user_pb_2=1, released) and blocked/filtered out when info_avi[112]=1 (user_pb_2=0, pressed) .

    Hope this answer your question.

    Thank you.

    Best Regards,

    ZulsyafiqH_Intel

ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi amildm,

I wish to follow up with you on this case. Do you still have further inquiries on this issue? I will remain this loop open for 2 days.

If we do not receive any response from you to the previous answer that I have provided.

This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread.

Thank you


Best Regards,

ZulsyafiqH_Intel


amildm's avatar
amildm
Icon for Contributor rankContributor
3 years ago

I'm going to test the proposed configuration on the board till end of the week, so meanwhile please don't close the case, thanks!