Forum Discussion
Contributor[HDMI IP] info_avi[112] control bit is assigned to Virtual Pin -> why?
Hi amildm,
Good day.
>Will the infoframe packet be sent out when info_avi[112]=1and blocked/filtered out when info_avi[112]=0?
I believe the above statement is incorrect.
Based on the Cyclone 10GX schematic file:
C10gx Schematic file
and the HDMI IP User Guide:
HDMI IP User Guide
when info_avi=1, it will not insert the Infoframe.
With that, the Infoframe packet will be sent out when info_avi[112]=0 (user_pb_2=1, released) and blocked/filtered out when info_avi[112]=1 (user_pb_2=0, pressed) .
Hope this answer your question.
Thank you.
Best Regards,
ZulsyafiqH_Intel
Frequent ContributorHi amildm,
Thank you for reaching out.
Yes, you are correct, the info_avi[112] is the control bit.
After checking from my side, from file c10_hdmi2_demo.v, line 481:
.info_avi ({~user_pb_2, tx_info_avi}),
From file c10_hdmi2_demo.qsf, the info_avi[112] control bit assigned to pin AH2.
.qsf
May I know your Quartus software version?
Thank you.
Best Regards,
ZulsyafiqH_Intel
ContributorI'm using the Quartus v19.3, in the generated by me Example Design this pis is assigned to Virtual Pin.
Why this signal is assigned to the external pin? What purpose for?
