GTS PMA/FEC Direct Transceiver Streaming

Hi,

I believe that your initial question of this thread has been addressed, I now transition this thread to community support. Feel free to open a new thread on bring up the GTS design in Terasic devkit as discussed previously.

Hi,

Thank you for the update. From what I understand, you've commented out the two lines in the .qsf file before proceeding with your own assignments based on the Terasic devkit. However, you still observe issue when running the loopback tests using the TCL script. Given the complexity of the current setup, it might be helpful to take a step back and explore a simpler design or configuration to isolate the issue more effectively. As you may know, the GTS PHY example design was validated using the Altera devkit.

Since this thread originally focused on data streaming, and our latest discussion is branching into different area, would you mind opening a new thread for this topic on bring up the GTS design in Terasic devkit? This will help us keep the discussions organized and make future reference easier. Once you've created the new thread, please share the link with me so we can continue the investigation there.

In the meantime, you might consider the following steps:

1. Check XCVR Routing: Confirm whether your Terasic devkit has XCVR channels routed to the FMC+ connectors.

2. Start with a Known Example: If yes, try using the "1 x 1G PMA Direct Mode (System PLL Clocking) with Custom Cadence" example design. Assign the pins ie resets, clock, XCVR and etc accordingly and perform an external loopback using the FMC+ loopback card.

3. Fixed data pattern: You can send fixed data pattern to the TX ie 0xBC... to ease the debugging and monitoring at the RX parallel output after external loopback.

4. Add SignalTap: Include SignalTap in your design to monitor key status signals such as GTS resets, ready, pll_locked, CDR lock status, freq_valid, etc. Refer to Figure 88 in the GTS User Guide for guidance on which signals to observe.

5. Run and Capture: Deploy the design on the Terasic devkit and capture the SignalTap results.

6. Compare and Debug: Compare the captured signals with the original simulation results from the example design. If you notice any anomalies, feel free to share the SignalTap capture for further analysis.

Looking forward to your findings in the new thread. Let me know if you have any concerns or need assistance setting it up.

Hi,

Sorry about the image display issue. I am trying to refer the following section "6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design" as in the GTS Transceiver PHY User Guide: Agilex 5 FPGAs and SoCs user guide. I extract some of the texts from the user guide as following. You may double check on the commenting out specific 2 lines in the .qsf file.

"You can perform hardware testing of the example design on the Agilex 5 FPGA ESeries

065B Premium Development Kit (ES1) board. You must select this

development kit in the Select Board setting in the Example Design tab of the IP

GUI, so that the reference clock and channel pin assignments are generated for the

development kit’s hardware design by the Quartus Prime software in the .qsf file.

If you require to change the pin assignments of the example design, you can comment

the following lines in the example_design.qsf file.

#set_global_assignment -name POST_MODULE_SCRIPT_FILE

"quartus_sh:board_assignments.tcl"

#set_global_assignment -name PRE_FLOW_SCRIPT_FILE

"quartus_sh:board_assignments.tcl"

After you have commented out the lines, you can set the pin assignments according to

your board setup and the assignments are reflected in the example design."

Please let me know if the issue still persists after you tested the above.Thank you.

Hi,

Just to add that in case you are not using the devkit as mentioned in the user guide, then you should also take note of the following steps from user guide before starting your own pin assignment:

Hi,

Thanks for your update. As I compared your Terminal printout when running the example design, I notice some discrepancies between yours vs the one shown in the user guide.

Yours:

% run_test_silb

-----------------------------------------------------------

-----------------------------------------------------------

Link is not UP

-----------------------------------------------------------

Apply RX reset: 0x00000022

Number of lanes : 1

1. 0x6A040

2. 0x0006a040

Polling Successfull Bit 15: 0x000001 , Bit 14: 0x000000

1. 0x62040

2. 0x00062040

Polling Successfull Bit 15: 0x000000 , Bit 14: 0x000000

Release reset: 0x00000000

Number of lanes : 1

Serial loopback on Lane# 0 is enabled

PHY IP Setting : 0x0002c067

Scratch Register : 0x00000000

Soft Rst Crtl : 0x00000000

TX/RX/AVMM Ready : 0x00000010

TX PLL Locked : 0x00000001

CDR LTR & LTD : 0x00000001

RX ignore LTD : 0x00000000

Alarm status : 0x00000000

The one from user guide:

I observed:

Few discrepancies that I observed:

1. Your test starts with "Apply RX reset: 0x00000022" seems only resetting the RX while the example in UG starts with "Apply TX-RX reset: 0x00000033 "

2. In your case, the TX/RX/AVMM Ready : 0x00000010 but the one in the UG = 0x00000030. As I understand it from the main.tcl, we will need the value of 0x00000030 to declare the link up.

puts "-----------------------------------------------------------"

if {$phy_reset_status_reg==0x30} {puts "Link is UP"} {puts "Link is not UP"}

puts "----

3. In your case, the "CDR LTR & LTD : 0x00000001 " but the one in the UG = 0x00010001. In your case, the CDR has not yet achieved LTD state, this is indicated by the bit[16] = 0.

Can you help to look into these discrepancies and cross check with your test case to see if can give further clue.

Another thing to double check with you is it that you are running the example design on Agilex 5 FPGA ESeries 065B Premium Development Kit (ES1) board? If not, then you may also need to double check on the pin assignment.

Please let me know if there is any concern. Thank you.

Hi,

Thanks for your update. Regarding the example design, just wonder if you could test with a simpler example design ie "1 x 1G PMA Direct Mode (System PLL Clocking) with Custom Cadence" to facilitate debugging. This design is running at lower data rate. You can first try running the simulation and then only on hardware.

Please let me know if you have any concern. Thank you.

Hi,

Regarding your run with the example design, could you please let me know which specific design from Table 87: Example Design Options you are using? I’d like to ensure we’re on the same page before providing further comments.

Please feel free to reach out if you have any concerns. Thank you.

Hi,

Regarding your following question about the reset, would you mind to further elaborate on what is referred by o_tx_clkout or o_rx_clkout components?

"Does there also include a place to explain how to connect resets for the o_tx_clkout / o_rx_clkout components?"

Please let me know if you have any concerns. Thank you.

Hi,

Regarding your specific question about whether this might cause issues when issuing DMA commands from the HPS:

"will this cause issues when issuing the DMA commands from the HPS?"

I’m afraid this falls outside my area of expertise, so I’m unable to provide a reliable answer.

Would you mind opening a new thread on the Forum specifically for this inquiry? That way, our relevant experts can take a closer look and assist you more effectively.

Please let me know if you have any concerns. Thank you.

Hi,

By the way, just wonder if you have had a chance to take a look at the example designs supported by the GTS XCVR PHY? You may refer to the GTS Transceiver PHY User Guide: Agilex 5 FPGAs and SoCs -> "Table 87. Example Design Options", for the list of available example designs. Then generate one which is closest to your target configuration to check on the PHY configuration and interconnection.

Please let me know if you have any further questions or concerns. Thank you.