Contributor
Regular ContributorHi,
By the way, just wonder if you have had a chance to take a look at the example designs supported by the GTS XCVR PHY? You may refer to the GTS Transceiver PHY User Guide: Agilex 5 FPGAs and SoCs -> "Table 87. Example Design Options", for the list of available example designs. Then generate one which is closest to your target configuration to check on the PHY configuration and interconnection.
Please let me know if you have any further questions or concerns. Thank you.
ContributorHi yes I did see this - after compilation, you can see here that after performing these commands in section 6.6:
% run_test_silb ----------------------------------------------------------- ----------------------------------------------------------- Link is not UP ----------------------------------------------------------- Apply RX reset: 0x00000022 Number of lanes : 1 1. 0x6A040 2. 0x0006a040 Polling Successfull Bit 15: 0x000001 , Bit 14: 0x000000 1. 0x62040 2. 0x00062040 Polling Successfull Bit 15: 0x000000 , Bit 14: 0x000000 Release reset: 0x00000000 Number of lanes : 1 Serial loopback on Lane# 0 is enabled PHY IP Setting : 0x0002c067 Scratch Register : 0x00000000 Soft Rst Crtl : 0x00000000 TX/RX/AVMM Ready : 0x00000010 TX PLL Locked : 0x00000001 CDR LTR & LTD : 0x00000001 RX ignore LTD : 0x00000000 Alarm status : 0x00000000 ----------------------------------- Value from issp reset probe is 0x45/0b1000101 -------------------------- Test Fail : Check the Link Status -------------------------- --------------- SILB TEST DONE ---------------- Apply RX reset: 0x00000022 Number of lanes : 1 1. 0x0A040 2. 0x0000a040 Polling Successfull Bit 15: 0x000001 , Bit 14: 0x000000 1. 0x02040 2. 0x00002040 Polling Successfull Bit 15: 0x000000 , Bit 14: 0x000000 Release reset: 0x00000000 Number of lanes : 1 Serial loopback on Lane# 0 is disabled
Maybe you have seen such an error before?
Many thanks!
