Forum Discussion
Hi,
Thanks for your update. As I compared your Terminal printout when running the example design, I notice some discrepancies between yours vs the one shown in the user guide.
Yours:
% run_test_silb
-----------------------------------------------------------
-----------------------------------------------------------
Link is not UP
-----------------------------------------------------------
Apply RX reset: 0x00000022
Number of lanes : 1
1. 0x6A040
2. 0x0006a040
Polling Successfull Bit 15: 0x000001 , Bit 14: 0x000000
1. 0x62040
2. 0x00062040
Polling Successfull Bit 15: 0x000000 , Bit 14: 0x000000
Release reset: 0x00000000
Number of lanes : 1
Serial loopback on Lane# 0 is enabled
PHY IP Setting : 0x0002c067
Scratch Register : 0x00000000
Soft Rst Crtl : 0x00000000
TX/RX/AVMM Ready : 0x00000010
TX PLL Locked : 0x00000001
CDR LTR & LTD : 0x00000001
RX ignore LTD : 0x00000000
Alarm status : 0x00000000
The one from user guide:
I observed:
Few discrepancies that I observed:
1. Your test starts with "Apply RX reset: 0x00000022" seems only resetting the RX while the example in UG starts with "Apply TX-RX reset: 0x00000033 "
2. In your case, the TX/RX/AVMM Ready : 0x00000010 but the one in the UG = 0x00000030. As I understand it from the main.tcl, we will need the value of 0x00000030 to declare the link up.
puts "-----------------------------------------------------------"
if {$phy_reset_status_reg==0x30} {puts "Link is UP"} {puts "Link is not UP"}
puts "----
3. In your case, the "CDR LTR & LTD : 0x00000001 " but the one in the UG = 0x00010001. In your case, the CDR has not yet achieved LTD state, this is indicated by the bit[16] = 0.
Can you help to look into these discrepancies and cross check with your test case to see if can give further clue.
Another thing to double check with you is it that you are running the example design on Agilex 5 FPGA ESeries 065B Premium Development Kit (ES1) board? If not, then you may also need to double check on the pin assignment.
Please let me know if there is any concern. Thank you.
- K6064 months ago
Contributor
Hi @CheePin_C_Intel,
I am running the example design on this board.
I have changed the pin assignments in parameter.tcl.
I have not changed any other pins - should I have?
Many thanks!