Forum Discussion
CheepinC_altera
Regular Contributor
5 months agoHi,
Thanks for your update. Regarding the example design, just wonder if you could test with a simpler example design ie "1 x 1G PMA Direct Mode (System PLL Clocking) with Custom Cadence" to facilitate debugging. This design is running at lower data rate. You can first try running the simulation and then only on hardware.
Please let me know if you have any concern. Thank you.
- K6065 months ago
Contributor
I just recompiled and tested this example, and found the same error!