FFT output scaling

I will be grateful if anyone can help me here, because I'm having a really hard time trying to sort things out.

I've already made a VHDL test bench to simulate a transform of a sinusoidal signal, but, I can't check if the result is correct, cause I'm not sure about the scaling procedure. The FFT Megacore user guide says I need to:

[LIST]Determine the length of the full scale register, according to the given table - DONE[/LIST]

[LIST]Map the output data to the appropriate location within the register, according to the exponent value - DONE[/LIST]

[LIST]Sign extend the data within the full scale register.[/LIST]

I'm stuck in the last item, because I don't know how to do that. The guide shows the following example:

case (exp)

6'b110101 : //-11 Set data equal to MSBs

begin

full_range_real_out[26:0] <= {real_in[15:0],11'b0};

full_range_imag_out[26:0] <= {imag_in[15:0],11'b0};

end

6'b110110 : //-10 Equals left shift by 10 with sign extension

begin

full_range_real_out[26] <= {real_in[15]};

full_range_real_out[25:0] <= {real_in[15:0],10'b0};

full_range_imag_out[26] <= {imag_in[15]};

full_range_imag_out[25:0] <= {imag_in[15:0],10'b0};

end

6'b110111 : //-9 Equals left shift by 9 with sign extension

begin

full_range_real_out[26:25] <= {real_in[15],real_in[15]};

full_range_real_out[24:0] <= {real_in[15:0],9'b0};

full_range_imag_out[26:25] <= {imag_in[15],imag_in[15]};

full_range_imag_out[24:0] <= {imag_in[15:0],9'b0};

end

.

.

.

endcase

I have no idea why, in the last case for example, the real_in[15] was assigned to full_range_real_out[26:25]. I thought I was supposed to left shift by 9 and fill the remaining bits with zeroes. Can somebody explain what is going on?