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Altera_Forum's avatar
Altera_Forum
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15 years ago

FFT output scaling

I will be grateful if anyone can help me here, because I'm having a really hard time trying to sort things out. I've already made a VHDL test bench to simulate a transform of a sinusoidal signa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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since 9 zero LSBs, then 15:0 and one sign bit make 26 bits while full range is 27 bits then sign bit repeated.

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So I must repeat the sign bit as many times as needed to match the full range width? For example, assume I would like to left shift by 5, so I do:

full_range_real_out [26:21] <= {real_in[15],real_in[15],real_in[15],real_in[15],real_in[15],real_in[15]};

full_range_real_out [20:0] <= {real_in [15:0],5'b0};