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Altera_Forum
Honored Contributor
15 years agoFFT output scaling
I will be grateful if anyone can help me here, because I'm having a really hard time trying to sort things out. I've already made a VHDL test bench to simulate a transform of a sinusoidal signa...
Altera_Forum
Honored Contributor
15 years agoI am not familiar with your fft scaling but here is explanation of your statements.
--- Quote Start --- full_range_real_out[26:25] <= {real_in[15],real_in[15]}; --- Quote End --- this is sign bit repeated twice to sign extend the value --- Quote Start --- full_range_real_out[24:0] <= {real_in[15:0],9'b0}; --- Quote End --- this is left shift by inserting 9 zeros on new LSBs. the original bits 15:0 are in effect multiplied by 2^9 since 9 zero LSBs, then 15:0 make 25 bits while full range is 27 bits then sign bit is repeated twice.