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Altera_Forum
Honored Contributor
Honored ContributorFFT output scaling
I will be grateful if anyone can help me here, because I'm having a really hard time trying to sort things out. I've already made a VHDL test bench to simulate a transform of a sinusoidal signa...
Altera_ForumHonored Contributor
Honored Contributori think all of the fixed point DSP IP uses 2's complement
