Exported MSI conduit on A10 PCIe AVMM IP is non-functional

The A10 PCIe IP core allows you to export msi interrupt signals, msi_interface[81:0] and msi_control[15:0]. These signals are described in UG-01145_AVMM document and are required if you are going to write your own MSI interrupt handler. These two exported conduits are supposed to reflect the msi configuration space registers, specifically address 0x50 thru 0x5C. The root complex writes to these registers to enable MSI interrupts and provides the endpoint with MSI information like allocated number of vectors, message address and message data. The problem is, this information is not being updated on these two conduits after the root complex writes to these configuration space registers. Using signal tap I can see the data on these two conduit ports and using some application software I can read the MSI registers in configuration space. The conduit interfaces are not being updated. For this PCIe AVMM application, we are using 64-bit addressing and MSI interrupts with 16 vectors requested. The documented results are provided below.

msi_control[15:0] = 0x0088

msi_interface[81:0] = 0x0000000000000

MSI Configuration Registers are:

Address 0x50 = 0x0089_7805 (Capability, Next Pointer and Message Control)

Address 0x54 = 0xFEE0_0000 (Lower 32-bits of the MSI Address)

Address 0x58 = 0x0000_0000 (Upper 32-bits of the MSI Address)

Address 0x5C = 0x0000_40A9 (Message Data)

As you can see, the root complex has enabled MSI interrupts with 1 vector granted but this is not reflected on the MSI conduit signals. The exported MSI conduit bus is useless. By the way, this all works in simulation. I'm using Quartus Prime Pro version 18.1