Forum Discussion
New ContributorExported MSI conduit on A10 PCIe AVMM IP is non-functional
KhaiY,
I'm sorry, due to ITAR, IP and other matters, this design cannot be shared. Although it's easy enough to put together your own simple design. The fact is, the MSI conduit interface simulates properly in version 18.1, it's the actual hardware that don't work. Another interesting fact is that in earlier versions of Quartus the MSI conduit simulation did not work, which back then, when you could, I pulled a Altera ticket. So I'm not surprised to see the hardware non-functional.
Regular ContributorHi,
Is there any timing violation in the design?
Thanks
Best regards,
KhaiY
GStreHi,
There was never a timing violation, look at the failure condition. The default power-up state of the MSI configuration registers are reporting correctly but they are never updated after the root complex enumerates the FPGA endpoint. I know it would be convenient to write this off to operator error, don't see it.
