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GStre's avatar
GStre
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Exported MSI conduit on A10 PCIe AVMM IP is non-functional

The A10 PCIe IP core allows you to export msi interrupt signals, msi_interface[81:0] and msi_control[15:0]. These signals are described in UG-01145_AVMM document and are required if you are going to ...
  • GStre's avatar
    GStre
    5 years ago

    KhaiY,

    I'm sorry, due to ITAR, IP and other matters, this design cannot be shared. Although it's easy enough to put together your own simple design. The fact is, the MSI conduit interface simulates properly in version 18.1, it's the actual hardware that don't work. Another interesting fact is that in earlier versions of Quartus the MSI conduit simulation did not work, which back then, when you could, I pulled a Altera ticket. So I'm not surprised to see the hardware non-functional.

KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


If you can see the data on the conduit ports using signal tap and read the MSI registers in configuration space, I think there is no problem in the FPGA PCIe endpoint. The problem happens after the root complex enumeration and modifying the application code of the interrupt handler without Qsys regeneration fixed the problem.


Thanks

Best regards,

KhaiY