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suppamax
New Contributor
New ContributorEMIF on Agilex 5
Hi,
I am trying to generate a DDR4 controller for Agilex 5 E-series, but all I seem to get is an empty box.
The generated verilog files look like this
[max@parma Workarea]$ cat quartus_dummy/ddr4/ddr4_inst.v ddr4 u0 ( ); [max@parma Workarea]$ cat quartus_dummy/ddr4/ ddr4_bb.v ddr4.cmp ddr4.html ddr4_inst.vhd ddr4.qgsynthc ddr4.sopcinfo synth/ ddr4.bsf ddr4_generation.rpt ddr4_inst.v ddr4.ppf ddr4.qip ddr4.xml [max@parma Workarea]$ cat quartus_dummy/ddr4/synth/ddr4.v // ddr4.v // Generated using ACDS version 24.1 115 `timescale 1 ps / 1 ps module ddr4 ( ); ddr4_emif_ph2_mem_device_ddr4_220_gvofvjq emif_ph2_mem_device_ddr4_0 ( ); endmodule
Any idea what am I doing wrong?
Thanks
8 Replies
zhenruanSome questions about your issue:
1. Could you please share the ddr4_generation.rpt file?
2. Which Agilex 5 E device was used for the generation?
3. What kind of license files is used for Quartus?
Regards,
Aaron
suppamaxThe generation report says
Info: Generated by version: 24.1 build 115 Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /home/max/Workarea/quartus_dummy/ddr4.ip --block-symbol-file --output-directory=/home/max/Workarea/quartus_dummy/ddr4 --family="Agilex 5" --part=A5ED065BB32AE6SR0 Info: Finished: Create block symbol file (.bsf) Info: Info: Starting: Create HDL design files for synthesis Info: qsys-generate /home/max/Workarea/quartus_dummy/ddr4.ip --synthesis=VERILOG --output-directory=/home/max/Workarea/quartus_dummy/ddr4 --family="Agilex 5" --part=A5ED065BB32AE6SR0 Info: ddr4: "Transforming system: ddr4" Info: ddr4: "Naming system components in system: ddr4" Info: ddr4: "Processing generation queue" Info: ddr4: "Generating: ddr4" Info: ddr4: "Generating: ddr4_emif_ph2_mem_device_ddr4_220_gvofvjq" Info: ddr4: Done "ddr4" with 2 modules, 1 files Info: Finished: Create HDL design files for synthesis Info: Starting: Generate IP Core Documentation Info: No documentation filesets were found for components in ddr4. No files generated. Info: Finished: Generate IP Core DocumentationI am targeting Agilex 5: A5ED065BB32AE6SR0
I have installed the Agilex 5 no cost license (but I have not been able to complete the generation of the programming file of the NIOS-V example I've found, see here)
sstrellSuper Contributor
What do you have in the synth directory where you generated the IP? Also, have you tried generating an example design?
- suppamax
$ ll ddr4/synth/ total 4 -rw-rw-r--. 1 max max 182 Apr 8 23:05 ddr4.v $ cat ddr4/synth/ddr4.v // ddr4.v // Generated using ACDS version 24.1 115 `timescale 1 ps / 1 ps module ddr4 ( ); ddr4_emif_ph2_mem_device_ddr4_220_gvofvjq emif_ph2_mem_device_ddr4_0 ( ); endmoduleI haven't generated an example design containing a ddr controller. The only one I have found has no EMIF.
Could you recommend one?
- sstrellNo I mean have you generated an example design from the EMIF IP parameter editor?
- suppamax
The example design gives reasonable results, e.g.
$ cat ./emif_ph2_0_example_design/qii/ip/ed_synth/ed_synth_emif_ph2_0/synth/ed_synth_emif_ph2_0.v // ed_synth_emif_ph2_0.v // Generated using ACDS version 24.1 115 `timescale 1 ps / 1 ps module ed_synth_emif_ph2_0 ( input wire ref_clk_0, // ref_clk_0.clk input wire core_init_n_0, // core_init_n_0.reset_n input wire usr_async_clk_0, // usr_async_clk_0.clk output wire usr_rst_n_0, // usr_rst_n_0.reset_n input wire [29:0] s0_axi4_araddr, // s0_axi4.araddr input wire [1:0] s0_axi4_arburst, // .arburst input wire [6:0] s0_axi4_arid, // .arid input wire [7:0] s0_axi4_arlen, // .arlen input wire s0_axi4_arlock, // .arlock input wire [3:0] s0_axi4_arqos, // .arqos input wire [2:0] s0_axi4_arsize, // .arsize input wire s0_axi4_arvalid, // .arvalid input wire [3:0] s0_axi4_aruser, // .aruser input wire [2:0] s0_axi4_arprot, // .arprot input wire [29:0] s0_axi4_awaddr, // .awaddr input wire [1:0] s0_axi4_awburst, // .awburst input wire [6:0] s0_axi4_awid, // .awid input wire [7:0] s0_axi4_awlen, // .awlen input wire s0_axi4_awlock, // .awlock input wire [3:0] s0_axi4_awqos, // .awqos input wire [2:0] s0_axi4_awsize, // .awsize input wire s0_axi4_awvalid, // .awvalid input wire [3:0] s0_axi4_awuser, // .awuser input wire [2:0] s0_axi4_awprot, // .awprot input wire s0_axi4_bready, // .bready input wire s0_axi4_rready, // .rready input wire [255:0] s0_axi4_wdata, // .wdata input wire [31:0] s0_axi4_wstrb, // .wstrb input wire s0_axi4_wlast, // .wlast input wire s0_axi4_wvalid, // .wvalid input wire [63:0] s0_axi4_wuser, // .wuser output wire [63:0] s0_axi4_ruser, // .ruser output wire s0_axi4_arready, // .arready output wire s0_axi4_awready, // .awready output wire [6:0] s0_axi4_bid, // .bid output wire [1:0] s0_axi4_bresp, // .bresp output wire s0_axi4_bvalid, // .bvalid output wire [255:0] s0_axi4_rdata, // .rdata output wire [6:0] s0_axi4_rid, // .rid output wire s0_axi4_rlast, // .rlast output wire [1:0] s0_axi4_rresp, // .rresp output wire s0_axi4_rvalid, // .rvalid output wire s0_axi4_wready, // .wready output wire mem_ck_t_0, // mem_0.mem_ck_t output wire mem_ck_c_0, // .mem_ck_c output wire mem_cke_0, // .mem_cke output wire mem_odt_0, // .mem_odt output wire mem_cs_n_0, // .mem_cs_n output wire [16:0] mem_a_0, // .mem_a output wire [1:0] mem_ba_0, // .mem_ba output wire mem_bg_0, // .mem_bg output wire mem_act_n_0, // .mem_act_n output wire mem_par_0, // .mem_par input wire mem_alert_n_0, // .mem_alert_n output wire mem_reset_n_0, // .mem_reset_n inout wire [15:0] mem_dq_0, // .mem_dq inout wire [1:0] mem_dqs_t_0, // .mem_dqs_t inout wire [1:0] mem_dqs_c_0, // .mem_dqs_c input wire oct_rzqin_0, // oct_0.oct_rzqin input wire s0_axi4lite_clk, // s0_axil_clk.clk input wire s0_axi4lite_rst_n, // s0_axil_rst_n.reset_n input wire [26:0] s0_axi4lite_awaddr, // s0_axil.awaddr input wire s0_axi4lite_awvalid, // .awvalid output wire s0_axi4lite_awready, // .awready input wire [31:0] s0_axi4lite_wdata, // .wdata input wire [3:0] s0_axi4lite_wstrb, // .wstrb input wire s0_axi4lite_wvalid, // .wvalid output wire s0_axi4lite_wready, // .wready output wire [1:0] s0_axi4lite_bresp, // .bresp output wire s0_axi4lite_bvalid, // .bvalid input wire s0_axi4lite_bready, // .bready input wire [26:0] s0_axi4lite_araddr, // .araddr input wire s0_axi4lite_arvalid, // .arvalid output wire s0_axi4lite_arready, // .arready output wire [31:0] s0_axi4lite_rdata, // .rdata output wire [1:0] s0_axi4lite_rresp, // .rresp output wire s0_axi4lite_rvalid, // .rvalid input wire s0_axi4lite_rready, // .rready input wire [2:0] s0_axi4lite_awprot, // .awprot input wire [2:0] s0_axi4lite_arprot // .arprot ); ed_synth_emif_ph2_0_emif_ph2_610_ftp76oi emif_ph2_inst ( .ref_clk_0 (ref_clk_0), // input, width = 1, ref_clk_0.clk .core_init_n_0 (core_init_n_0), // input, width = 1, core_init_n_0.reset_n .usr_async_clk_0 (usr_async_clk_0), // input, width = 1, usr_async_clk_0.clk .usr_rst_n_0 (usr_rst_n_0), // output, width = 1, usr_rst_n_0.reset_n .s0_axi4_araddr (s0_axi4_araddr), // input, width = 30, s0_axi4.araddr .s0_axi4_arburst (s0_axi4_arburst), // input, width = 2, .arburst .s0_axi4_arid (s0_axi4_arid), // input, width = 7, .arid .s0_axi4_arlen (s0_axi4_arlen), // input, width = 8, .arlen .s0_axi4_arlock (s0_axi4_arlock), // input, width = 1, .arlock .s0_axi4_arqos (s0_axi4_arqos), // input, width = 4, .arqos .s0_axi4_arsize (s0_axi4_arsize), // input, width = 3, .arsize .s0_axi4_arvalid (s0_axi4_arvalid), // input, width = 1, .arvalid .s0_axi4_aruser (s0_axi4_aruser), // input, width = 4, .aruser .s0_axi4_arprot (s0_axi4_arprot), // input, width = 3, .arprot .s0_axi4_awaddr (s0_axi4_awaddr), // input, width = 30, .awaddr .s0_axi4_awburst (s0_axi4_awburst), // input, width = 2, .awburst .s0_axi4_awid (s0_axi4_awid), // input, width = 7, .awid .s0_axi4_awlen (s0_axi4_awlen), // input, width = 8, .awlen .s0_axi4_awlock (s0_axi4_awlock), // input, width = 1, .awlock .s0_axi4_awqos (s0_axi4_awqos), // input, width = 4, .awqos .s0_axi4_awsize (s0_axi4_awsize), // input, width = 3, .awsize .s0_axi4_awvalid (s0_axi4_awvalid), // input, width = 1, .awvalid .s0_axi4_awuser (s0_axi4_awuser), // input, width = 4, .awuser .s0_axi4_awprot (s0_axi4_awprot), // input, width = 3, .awprot .s0_axi4_bready (s0_axi4_bready), // input, width = 1, .bready .s0_axi4_rready (s0_axi4_rready), // input, width = 1, .rready .s0_axi4_wdata (s0_axi4_wdata), // input, width = 256, .wdata .s0_axi4_wstrb (s0_axi4_wstrb), // input, width = 32, .wstrb .s0_axi4_wlast (s0_axi4_wlast), // input, width = 1, .wlast .s0_axi4_wvalid (s0_axi4_wvalid), // input, width = 1, .wvalid .s0_axi4_wuser (s0_axi4_wuser), // input, width = 64, .wuser .s0_axi4_ruser (s0_axi4_ruser), // output, width = 64, .ruser .s0_axi4_arready (s0_axi4_arready), // output, width = 1, .arready .s0_axi4_awready (s0_axi4_awready), // output, width = 1, .awready .s0_axi4_bid (s0_axi4_bid), // output, width = 7, .bid .s0_axi4_bresp (s0_axi4_bresp), // output, width = 2, .bresp .s0_axi4_bvalid (s0_axi4_bvalid), // output, width = 1, .bvalid .s0_axi4_rdata (s0_axi4_rdata), // output, width = 256, .rdata .s0_axi4_rid (s0_axi4_rid), // output, width = 7, .rid .s0_axi4_rlast (s0_axi4_rlast), // output, width = 1, .rlast .s0_axi4_rresp (s0_axi4_rresp), // output, width = 2, .rresp .s0_axi4_rvalid (s0_axi4_rvalid), // output, width = 1, .rvalid .s0_axi4_wready (s0_axi4_wready), // output, width = 1, .wready .mem_ck_t_0 (mem_ck_t_0), // output, width = 1, mem_0.mem_ck_t .mem_ck_c_0 (mem_ck_c_0), // output, width = 1, .mem_ck_c .mem_cke_0 (mem_cke_0), // output, width = 1, .mem_cke .mem_odt_0 (mem_odt_0), // output, width = 1, .mem_odt .mem_cs_n_0 (mem_cs_n_0), // output, width = 1, .mem_cs_n .mem_a_0 (mem_a_0), // output, width = 17, .mem_a .mem_ba_0 (mem_ba_0), // output, width = 2, .mem_ba .mem_bg_0 (mem_bg_0), // output, width = 1, .mem_bg .mem_act_n_0 (mem_act_n_0), // output, width = 1, .mem_act_n .mem_par_0 (mem_par_0), // output, width = 1, .mem_par .mem_alert_n_0 (mem_alert_n_0), // input, width = 1, .mem_alert_n .mem_reset_n_0 (mem_reset_n_0), // output, width = 1, .mem_reset_n .mem_dq_0 (mem_dq_0), // inout, width = 16, .mem_dq .mem_dqs_t_0 (mem_dqs_t_0), // inout, width = 2, .mem_dqs_t .mem_dqs_c_0 (mem_dqs_c_0), // inout, width = 2, .mem_dqs_c .oct_rzqin_0 (oct_rzqin_0), // input, width = 1, oct_0.oct_rzqin .s0_axi4lite_clk (s0_axi4lite_clk), // input, width = 1, s0_axil_clk.clk .s0_axi4lite_rst_n (s0_axi4lite_rst_n), // input, width = 1, s0_axil_rst_n.reset_n .s0_axi4lite_awaddr (s0_axi4lite_awaddr), // input, width = 27, s0_axil.awaddr .s0_axi4lite_awvalid (s0_axi4lite_awvalid), // input, width = 1, .awvalid .s0_axi4lite_awready (s0_axi4lite_awready), // output, width = 1, .awready .s0_axi4lite_wdata (s0_axi4lite_wdata), // input, width = 32, .wdata .s0_axi4lite_wstrb (s0_axi4lite_wstrb), // input, width = 4, .wstrb .s0_axi4lite_wvalid (s0_axi4lite_wvalid), // input, width = 1, .wvalid .s0_axi4lite_wready (s0_axi4lite_wready), // output, width = 1, .wready .s0_axi4lite_bresp (s0_axi4lite_bresp), // output, width = 2, .bresp .s0_axi4lite_bvalid (s0_axi4lite_bvalid), // output, width = 1, .bvalid .s0_axi4lite_bready (s0_axi4lite_bready), // input, width = 1, .bready .s0_axi4lite_araddr (s0_axi4lite_araddr), // input, width = 27, .araddr .s0_axi4lite_arvalid (s0_axi4lite_arvalid), // input, width = 1, .arvalid .s0_axi4lite_arready (s0_axi4lite_arready), // output, width = 1, .arready .s0_axi4lite_rdata (s0_axi4lite_rdata), // output, width = 32, .rdata .s0_axi4lite_rresp (s0_axi4lite_rresp), // output, width = 2, .rresp .s0_axi4lite_rvalid (s0_axi4lite_rvalid), // output, width = 1, .rvalid .s0_axi4lite_rready (s0_axi4lite_rready), // input, width = 1, .rready .s0_axi4lite_awprot (s0_axi4lite_awprot), // input, width = 3, .awprot .s0_axi4lite_arprot (s0_axi4lite_arprot) // input, width = 3, .arprot ); endmodule - zhenruan
I generated the ddr4 ip and its example design for device A5ED065BB32AE6SR0 with Agilex 5 E no-cost license and found no issue.
Please make sure the no-cost license had been acquired successfully. For Quartus Linux version you may need to set the proxy server for it and then apply the no-cost license.
Regards,
Aaron
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