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suppamax's avatar
suppamax
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2 years ago

EMIF on Agilex 5

Hi, I am trying to generate a DDR4 controller for Agilex 5 E-series, but all I seem to get is an empty box. The generated verilog files look like this [max@parma Workarea]$ cat quartus_dummy/d...
Memory
suppamax's avatar
suppamax
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2 years ago

The generation report says

Info: Generated by version: 24.1 build 115
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/max/Workarea/quartus_dummy/ddr4.ip --block-symbol-file --output-directory=/home/max/Workarea/quartus_dummy/ddr4 --family="Agilex 5" --part=A5ED065BB32AE6SR0
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/max/Workarea/quartus_dummy/ddr4.ip --synthesis=VERILOG --output-directory=/home/max/Workarea/quartus_dummy/ddr4 --family="Agilex 5" --part=A5ED065BB32AE6SR0
Info: ddr4: "Transforming system: ddr4"
Info: ddr4: "Naming system components in system: ddr4"
Info: ddr4: "Processing generation queue"
Info: ddr4: "Generating: ddr4"
Info: ddr4: "Generating: ddr4_emif_ph2_mem_device_ddr4_220_gvofvjq"
Info: ddr4: Done "ddr4" with 2 modules, 1 files
Info: Finished: Create HDL design files for synthesis
Info: Starting: Generate IP Core Documentation
Info: No documentation filesets were found for components in ddr4. No files generated.
Info: Finished: Generate IP Core Documentation

I am targeting Agilex 5: A5ED065BB32AE6SR0

I have installed the Agilex 5 no cost license (but I have not been able to complete the generation of the programming file of the NIOS-V example I've found, see here)