Forum Discussion
suppamax
New Contributor
New ContributorEMIF on Agilex 5
Hi, I am trying to generate a DDR4 controller for Agilex 5 E-series, but all I seem to get is an empty box. The generated verilog files look like this [max@parma Workarea]$ cat quartus_dummy/d...
sstrell
Super Contributor
Super ContributorWhat do you have in the synth directory where you generated the IP? Also, have you tried generating an example design?
