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suppamax's avatar
suppamax
Icon for New Contributor rankNew Contributor
2 years ago

EMIF on Agilex 5

Hi, I am trying to generate a DDR4 controller for Agilex 5 E-series, but all I seem to get is an empty box. The generated verilog files look like this [max@parma Workarea]$ cat quartus_dummy/d...
Memory
suppamax's avatar
suppamax
Icon for New Contributor rankNew Contributor
2 years ago
$ ll ddr4/synth/
total 4
-rw-rw-r--. 1 max max 182 Apr  8 23:05 ddr4.v
$ cat ddr4/synth/ddr4.v 
// ddr4.v

// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module ddr4 (
	);

	ddr4_emif_ph2_mem_device_ddr4_220_gvofvjq emif_ph2_mem_device_ddr4_0 (
	);

endmodule

I haven't generated an example design containing a ddr controller. The only one I have found has no EMIF.

Could you recommend one?

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    2 years ago
    No I mean have you generated an example design from the EMIF IP parameter editor?